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Advanced
CAT28HT256
256K-Bit CMOS PARALLEL E PROM
2
Extended Temperature: 170C
FEATURES
s Fast Read Access Times: 200/250 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation:
-Active: 30 mA Max. -Standby: 150 A Max.
s Simple Write Operation:
-1 to 64 Bytes in 10ms -Page Load Timer
s End of Write Detection:
-On-Chip Address and Data Latches -Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
-Toggle Bit -DATA Polling DATA
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention
-10ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28HT256 is a fast, low power, 5V-only CMOS parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28HT256 features hardware and software write protection as well as an internal Error Correction Code (ECC) for extremely high reliability. The CAT28HT256 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin Ceramic DIP package.
BLOCK DIAGRAM
A6-A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
5096 FHD F02
I/O0-I/O7
A0-A5
ADDR. BUFFER & LATCHES
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Advanced
PIN CONFIGURATION
CERDIP Package (D)
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
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PIN FUNCTIONS
Pin Name A0-A14 I/O0-I/O7 CE OE WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable 5V Supply Ground No Connect
RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(2) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 104 or 105 100 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC +1V.
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CAT28HT256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +150C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA D.C. OPERATING CHARACTERISTICS
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
VCC = 5V 10%, unless otherwise specified. (Temperature 0C to 170C) Limits Symbol ICC ICCC(3) ISB ISBC(4) ILI ILO VIH(4) VIL(3) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 3.5 -10 -10 2 -0.3 2.4 0.4 Min. Typ. Max. 30 25 1 300 20 20 VCC +0.3 0.8 Units mA mA mA A A A V V V V V IOH = -400A IOL = 2.1mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = OE = VILC, f = 1/tRC min, All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) VILC = -0.3V to +0.3V. (4) VIHC = VCC -0.3V to VCC +0.3V.
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Advanced
A.C. CHARACTERISTICS, Read Cycle VCC = 5V 10%, unless otherwise specified. (Temperature 0C to 170C) 28HT256-20 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(4) tOHZ(1)(4) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. Max. 200 200 200 80 0 0 50 50 28HT256-25 Min. 250 250 250 100 Max. Units ns ns ns ns ns ns ns ns ns
A.C. CHARACTERISTICS, Write Cycle VCC = 5V 10%, unless otherwise specified. (Temperature 0C to 170C) 28HT256-20 Symbol tWC tAS tAH tCS tCH tCW(2) tOES tOEH tWP(2) tDS tDH tINIT(1) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up 0 75 0 0 100 0 0 100 50 10 5 0.1 10 100 Min. Max. 10 0 75 0 0 100 0 0 100 50 10 5 0.1 10 100 28HT256-25 Min. Max. Units 10 ms ns ns ns ns ns ns ns ns ns ns ms s
tBLC(1)(3) Byte Load Cycle Time
Note: (1) This parameter is tested intitially and after a design or process change that affects the parameter.. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
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Advanced
CAT28HT256
DEVICE OPERATION
Read Data stored in the CAT28HT256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Figure 1. A.C. Testing Input/Output Waveform(1)
2.4 V INPUT PULSE LEVELS 0.45 V
Note: (1) Input rise and fall times (10% and 90%) < 10 ns.
Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms.
2.0 V REFERENCE POINTS 0.8 V
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5096 FHD F04
Figure 3. Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA tOHZ tHZ DATA VALID
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Page Write The page write mode of the CAT28HT256 (essentially an extended BYTE WRITE mode) allows from 1 to 64 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the byte-write time by a factor of 64. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 64 byte temporary buffer. The page address where data is to be written, specified by bits A6 to A14, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A5 Figure 4. Byte Write Cycle [WE Controlled] WE
(which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page.
tWC ADDRESS tAS tCS CE tAH tCH
OE tOES WE tBLC DATA OUT HIGH-Z tWP tOEH
DATA IN
DATA VALID tDS tDH
Figure 5. Byte Write Cycle [CE Controlled] CE
tWC ADDRESS tAS tAH tCW CE tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH tBLC
DATA IN
DATA VALID tDS tDH
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Advanced
CAT28HT256
DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0-I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O's will output true data during a read cycle. Figure 6. Page Mode Write Cycle
OE
Toggle Bit In addition to the DATA Polling feature of the CAT28HT256, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device.
CE t WP WE t BLC
ADDRESS t WC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2
5096 FHD F10
Figure 7. DATA Polling
ADDRESS
CE
WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X
5096 FHD F11
tOE
tOES
Figure 8. Toggle Bit
WE
CE tOEH OE tOE tOES
I/O6
(1) tWC
(1)
Note: (1) Beginning and ending state of I/O6 is indeterminate.
5096 FHD F12
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CAT28HT256
HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28HT256. (1) VCC sense provides for write protection when VCC falls below 3.5V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high.
Advanced
(4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28HT256 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28HT256 is in the standard operating mode).
Figure 9. Write Sequence for Activating Software Data Protection
WRITE DATA: ADDRESS: AA 5555
Figure 10. Write Sequence for Deactivating Software Data Protection
WRITE DATA: ADDRESS: AA 5555
WRITE DATA: ADDRESS:
55 2AAA
WRITE DATA: ADDRESS:
55 2AAA
WRITE DATA: ADDRESS:
A0 5555
WRITE DATA: ADDRESS:
80 5555
SOFTWARE DATA (12) (1) PROTECTION ACTIVATED
WRITE DATA: ADDRESS:
AA 5555
WRITE DATA:
XX
WRITE DATA: ADDRESS:
55 2AAA
TO ANY ADDRESS
WRITE LAST BYTE TO LAST ADDRESS
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WRITE DATA: ADDRESS:
20 5555
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Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation.
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Advanced
To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. Figure 11. Software Data Protection Timing
DATA ADDRESS CE tWP WE tBLC AA 5555 55 2AAA A0 5555 BYTE OR PAGE WRITES ENABLED tWC
CAT28HT256
To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence.
5096 FHD F13
Figure 12. Resetting Software Data Protection Timing
DATA ADDRESS CE DEVICE UNPROTECTED WE
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AA 5555
55 2AAA
80 5555
AA 5555
55 2AAA
20 5555
tWC
SDP RESET
ORDERING INFORMATION
Prefix CAT Device # 28HT256 Suffix H D -20
Product Number
Package D: CERDIP
Optional Company ID
Endurance Blank = 10,000 Cycle H = 100,000 Cycle
Speed 20: 200ns 25: 250ns
28HT256 F16
Notes: (1) The device used in the above example is a CAT28HT256HD-20 (100,000 Cycle Endurance, CERDIP, 200 ns Access Time).
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